1.
Design and Analysis of CMOS PLL Clock Generator;
CMOS锁相环时钟发生器的设计与研究
2.
single-phase clock generator
单相时钟脉冲发生器
3.
A True Random Number Generator Based on PLL
一种基于锁相环的真随机数发生器
4.
Design of Phase-locked Loop for USB2.0 Application;
应用于USB2.0时钟数据恢复的锁相环设计
5.
The Design of a Phase-Locked Loop Used in a DSP Clock System;
一种用于DSP时钟系统的锁相环的设计
6.
Design of Digital Phase Locked Loop Used in SDH Equipment Clock
SDH设备时钟中的数字锁相环设计
7.
Design of a High-speed Integrated PLL for Clock Recovery Circuit
用于时钟恢复电路的高速集成锁相环设计研究
8.
Design of SDH/SONET Tributary Clock Jitter Attenuation Digital Phase Lock Loop
SDH/SONET支路时钟抖动衰减数字锁相环设计
9.
boosted-high level clock generator
升压高电平时钟发生器
10.
TV station clock mark generator
电视台时钟台标发生器
11.
DRCG Direct Rambus clock generator
直接RAMBUS时钟发生器
12.
clock pulse generator
时钟脉冲发生器同步脉冲发生器
13.
Research on Adpll-Basedtime Digital Converter
基于全数字锁相环的时间数字转换器的研究
14.
New Method of Generating GPS High Accuracy Synchronous Clock Based on the Digital Phase-lock Principle
基于数字锁相原理的GPS高精度同步时钟产生新方法
15.
Design and Implementation of Wideband High-Performance TIADC Clock Generator
一种宽带高性能TIADC时钟发生器
16.
Scheme of Fast Self-Calibration for a FPGA Chip Clock Generator
FPGA片上时钟发生器快速自校准方案
17.
A New Mixed-mode Design of DCM Clock Delay Locked Loop
一种新型混合信号时钟延时锁定环电路设计
18.
Research of PLL Frequency Synthesizer for 802.11 Transceiver;
应用于802.11收发器的锁相环频率合成器的技术研究