1.
Design and Implementation of Configurable Parallet BCH Decoder
可配置并行BCH译码器的设计与实现
2.
High-Speed Parallel BCH Decoder Circuit in VLSI
高速并行BCH译码器的VLSI设计
3.
An area-efficient parallel BCH decoder supporting foresighted error search
一种支持预搜索的面积紧凑型BCH并行译码电路
4.
Realization of the Encoder of BCH(23,12) Code Based on FPGA;
基于FPGA的BCH(23,12)码编译码器的实现
5.
Research and FPGA Implementation of BCH Encoder and Decoder in Digital Television Broadcasting System;
数字电视传输系统中BCH码编/译码器的研究与FPGA实现
6.
Design and implementation of a full parallel LDPC decoder
LDPC码全并行译码器的设计与实现
7.
The Optimization and Application of Decoding Algorithm of Binary BCH Code;
二元BCH码译码算法的优化与应用
8.
A Coding and Decoding Algorithm and its implementation of shortened BCH Codes(16,8,5)
缩短BCH码(16,8,5)编译码算法及其实现
9.
The Implementation of BCH Hardware Decoder on BM Algorithm
基于BM算法的BCH码的译码硬件实现
10.
Design and Implementation of Hign Throughput Parallel Turbo Decoder;
高速并行Turbo译码器的设计与实现
11.
FPGA Implementation of a Novel Parallel Turbo Encoder/Decoder;
一种新型并行Turbo编译码器的FPGA实现
12.
Design and Realization of Improved All-parallel Viterbi Decoder
改进型全并行Viterbi译码器设计与实现
13.
The CODEC can be used to carry on coding transmission and decoding reception in parallel with code error detection and bit synchronized signal recovering.
该编译码器能进行并行发送编码和接收译码,并带有误码检测和位同步提取的功能。
14.
The change bit one-by-one decode method for BCH and its application in GPON system
BCH码逐位取反译码方法及其在GPON系统中的应用
15.
Parametric Design of BCH/RS Coder/Decoder;
参数化的BCH/RS编解码器设计
16.
Bose-Chaudhuri-HocQuenghem code
错误纠正码，bch 码
17.
Parallel complementary decoding based on OSD and Chase
OSD和Chase的并行互补译码
18.
Research on Construction, Parallel Concatenation and Decoder Design of Low-Density Parity-Check Codes;
低密度奇偶校验码构造、并行级联与译码器设计的研究