1.
A New Mixed-mode Design of DCM Clock Delay Locked Loop
一种新型混合信号时钟延时锁定环电路设计
2.
Design of the Real Time Clock Chip with the Alarm-Delay Protection;
具有报警延时保护功能的实时时钟芯片的设计
3.
Supports external wait signal to expend the buS cycle.
支持外部等待时钟信号延长总线周期。
4.
Simulation Analysis of MEMS-Based Inertial Delay Pendulum Mechanism
基于MEMS的钟表惯性延时机构仿真分析
5.
Clock Synchronization Estimation of Wireless Sensor Networks with Exponential Delay
基于指数时延的无线传感器网络时钟同步估计
6.
A clock and data recovery method based on phase detector implemented by delay chain in FPGA
利用FPGA延时链实现鉴相器时钟数据恢复
7.
Finally, the time delay compensation controller is designed for NCS when the controller is event-driven.
最后,研究了控制器为时钟驱动时网络控制系统的时延补偿控制。
8.
the bank has extended it's service time to 10 o'clock in the evening.
银行已经将营业时间延长至晚上10点钟了 。?
9.
Network Clock Synchronization Based on Delay and Ringed Topology;
基于延迟和环状拓扑的网络时钟同步系统
10.
the chime of church; bells/of the clock
教堂钟[时钟]的钟声.
11.
chronometer time plus watch time
天文钟时间加钟表时间
12.
chronometer time minus watch time
天文钟时间减钟表时间
13.
Fault Detection for Networked Control Systems with Long Time-delay of Asynchronous Clock
具有长时延和异步时钟的网络控制系统的故障检测
14.
The single journey time on a bus route is25 mins, and5 mins is allowed in the schedule before the next journey to recover from any late running.
巴士完成一次线路所用时间为25分钟，在下一班出发前允许有5分钟的时间以弥补可能的延误。
15.
Due to the concern of process variation, the delay of each clock buffer is treated as a range instead of a single value.
在制程变异上面，每个时钟缓冲器的延迟值被表示为一个范围值。
16.
as far as I know, the bank has extended its service time to 10 o'clock in the evening.
据我所知，银行已经将营业时间延长至晚上10点钟了。
17.
a clock regulated by a pendulum.
用钟摆调整时间的钟。
18.
The clock chimed twelve o'clock.
时钟鸣报十二点钟。