1.
Research on Library Building of VDSM Memory;
深亚微米工艺下的Memory建库技术研究
2.
Research on the IP Design Methodology Based on the DSM Technology;
基于深亚微米工艺的IP设计技术研究
3.
Research on Timing Modeling of VDSM IC Cells;
深亚微米工艺下的单元时序建模研究
4.
Study of Parameters Limiting ESD Performance in Deep Submicron process
深亚微米工艺ESD电路设计参数研究
5.
Domino Logic Circuit Design Based on Submicron Technology
基于深亚微米工艺的多米诺逻辑电路设计
6.
Study on Crosstalk and Its Effect of Interconnect in VDSM
超深亚微米工艺下互连线串扰及其影响研究
7.
FOD Based ESD Protection Devices in Deep Sub-micron Technology
深亚微米工艺中场氧器件静电防护能力的研究
8.
Study and Application of IDDQ Test Technology for DSM Device;
深亚微米工艺下芯片的IDDQ测试技术的研究及应用
9.
The Analysis and Realization of Routing Algorithm for Crosstalk Reduction under Deep Submicron Technology;
深亚微米工艺下串扰优化的布线算法分析与实现
10.
Static Timing Analysis Methodology and Research for Sign-off under UDSM Technology;
深亚微米工艺下签核（sign-off）静态时序分析方法与研究
11.
A resistance macromodel for deep-submicron process epi-type substrate based on the 2D device simulation is presented.
提出了一种基于二维器件模拟的深亚微米工艺外延型衬底的电阻宏模型。
12.
Research on Logic Parameter Extraction and Modeling of Standard Cell and Memory Under Dsm Technology;
深亚微米工艺条件下标准单元和存储器逻辑参数提取及建模技术研究
13.
The Research of Ni-SALICIDE Process for the Application to Deep Sub-micron CMOS Devices;
适用于深亚微米CMOS器件的Ni自对准硅化物工艺的研究
14.
Microarc Oxidation Coating of the Sub-Micron Holes
亚微米级孔径微弧氧化膜层工艺研究
15.
As the technology proceeds to DSM, the delay of interconnect has been the dominant portion in all delays.
当工艺水平发展到深亚微米级,互连线时延比重已经占据总时延的绝大部分。
16.
Research and Implementation of the System Structure of a Lithography Simulation Tool in VDSM;
超深亚微米下一种光刻仿真工具的系统框架研究及其实现
17.
The Relationship between Structuer and Properties with the Deformation Thchnics of Submicron Grains Cu-5Cr Composite Material;
亚微米晶Cu-5Cr复合材料变形工艺与组织性能关系的研究
18.
Progress in the Developments of DSM IC Technology in the 21~(st) Century
21世纪深亚微米芯片技术的新进展