1.
A novel interconnect delay and slew model based PDF Interpretation for 90nm technology
一种基于概率解释的新型互连线时延Slew模型
2.
Interconnection delay has become a dominant factor in IC design.
互连线时延是集成电路设计中非常重要的影响因素。
3.
In order to decrease the interconnect delay, it′ s a common and effective way to insert buffers in it.
为了减小互连线时延,缓冲器插入是当前一种常见且有效的方法。
4.
Stochastic collocation method for interconnect delay estimation in the presence of process variations
工艺参数扰动下互连线时延的随机点匹配评估算法
5.
As the technology proceeds to DSM, the delay of interconnect has been the dominant portion in all delays.
当工艺水平发展到深亚微米级,互连线时延比重已经占据总时延的绝大部分。
6.
Statistical RLC Interconnect Delay Considering Process Variations
考虑工艺波动影响的RLC互连统计延时
7.
Extreme value analysis of RLC interconnect delay induced by process variations
工艺波动致RLC互连延时极值分析
8.
Research on RLC Interconnect Delay Variation Induced by Thermal Effects
热效应致RLC互连延时变化研究(英文)
9.
Modeling of interconnects and delay analysis in the presence of Random VLSI process variations
VLSI随机工艺变化下互连线建模与延迟分析
10.
Statistical Interconnect Timing Models Using Symbolic Moments
基于符号化矩的互连线统计时序建模
11.
Stochastic modeling of distributed parameters and analysis of interconnect delay in the presence of process variations
工艺变化下互连线分布参数随机建模与延迟分析
12.
State Space Models of RLGC Interconnect with Super High Order in Time Domain and Its Research
超高阶的RLGC互连线时域状态空间模型及其研究
13.
interconnect tape
带有引线架的互连带
14.
DO NOT ALLOW JUMPER CABLE CLAMPS TO TOUCH EACH OTHER WHEN CONNECTED TO A BOOSTER SOURCE.
在连接到一个增压器源时，千万不要让跨接线组夹相互接触。
15.
Interconnect Models and Layout-Oriented Design Methods and Delay/Power Optimization Methods in SOC Design;
SOC中的连线模型与面向布局布线的设计方法及时延/功耗优化方法研究
16.
Extends all sides of the 3-D effect parallel to one another
三维效果平行线的所有侧面互相延伸
17.
Time Delay Estimation Based on Cross-correlation and Multiple Signal Classification
基于互相关和MUSIC算法的时延估计
18.
Time-delay Estimation Based on Generalized Cross Correlation
基于广义互相关算法的时延估计研究