1.
0ne-cycle ASIC Implementation of Interleaving Address Generator Based on Computation;
单周期基于计算的交织地址产生器的ASIC实现
2.
A Design of Address Generation Unit of Digital Signal Processor
一种数字信号处理器地址产生单元的设计
3.
The controller comprises an address generator having a plurality of base address generators, and a read/ write control circuitry.
控制器包含一具有多个基本位址的位址产生器，和一读/写控制电路。
4.
address register
【计】 地址寄存器
5.
interrupt (address) register
中断(地址)寄存器
6.
boundary (address) register
边界(地址)寄存器
7.
Classification of stone tools and agricultural production-A review of Shi Lao Duang neolithic site in Ying De County Guang Dong Province
广东英德史老墩遗址的石器分类与农业生产——兼论广东地区新石器时代的农业发展
8.
Consider a program that generates name and address labels.
设想一个产生姓名和地址标签的程序。
9.
The Design and Realization of Data Address Generation of X-DSP
X-DSP数据地址产生部件的设计与实现
10.
controller bus address register
控制器总线地址寄存器
11.
BSAR (Buffer Storage Address Register)
缓冲存贮器地址寄存器
12.
memory address select register
存储器地址选择寄存器
13.
memory buffer address register
存储器缓冲地址寄存器
14.
EMAR (Experimental Memory Address Register)
实验存贮器地址寄存器
15.
experimental memory address register
实验存储器地址寄存器
16.
The Study of Real Estate Siting Based on the Green Space s Construction;
基于生态绿地建设的房地产开发选址研究
17.
RCD Row to Cas Delay
行地址到列地址控制器延迟时间
18.
The fetcher also generates a search address for output to the branch target buffer.
指令读取器亦产生搜寻位址输出至分支目标缓冲器中。