1.
A High-speed,Low-power pipelined16×16-bit mul-tiplier based on0.5μm CMOS Process is designed using Booth encoder,Wallace tree.
提出了一种16×16位的高速低功耗流水线乘法器的设计。
2.
The Design of High Speed Pipeline Floating Point Multiplier Based on FPGA
基于FPGA的高速流水线浮点乘法器设计
3.
Monolithic Integrated 16×16 bit Multiplier Operating in Parallel and Pipeline
单片集成并行流水线操作16×16位数字乘法器
4.
18×18 Parallel and Pipeline Multiplier Chip Design
18×18并行流水乘法器芯片设计
5.
The Design of 10bits 10MSPS Pipelined A/D Convertor and the Algorithm Modification;
10位、10MSPS流水线结构A/D转换器的设计和算法改进
6.
The Implementation of a FFT Processor Based on FPGA and CORDIC Algorithm
基于FPGA与流水线CORDIC算法的FFT处理器的实现
7.
Research on From-to Chart optimizing method based on pipelined production process
基于“流水线”的机器排序优化从至图分析方法
8.
Gain Calibration for Multi-Bit Stages in Pipelined A/D Converter
一种流水线A/D转换器Multi-bit级增益误差校正方法
9.
Improved Digital Calibration Arithmetic for Pipelined A/D Converter
用于流水线A/D转换器的改进型数字自校准算法
10.
A New Method of Non-linear Least Square Estimation of Rheological Parameter for Drilling Fluid
钻井液流变参数的非线性最小二乘估计算法
11.
The Calculation of AOF of Gas Well Based on Non-linear Least Squares Method
基于非线性最小二乘法的气井无阻流量计算
12.
Bend Stream-tube Method of Calculating the Hydrodynamic Performance of Cycloidal Propeller and Rotor;
计算摆线推进器和水轮机水动力性能的弯曲流管法
13.
Current Mode Pipelined CMOS A/D Converter;
电流模式的流水线结构的CMOS A/D转换器
14.
Application of Motion Analysis in the Teaching of the Design of Speed Reducer Assembly Line
动作分析法在减速器装配流水线设计教学中的应用
15.
exploring the sea bed in a submersible
乘潜水器探测海底.
16.
Digit-serial binary field multiplier based on Mastrovito multiplication
基于Mastrovito乘法的字串行特征二域乘法器
17.
Design of 10bit 40MHz Pipelined Analog-to-Digital Converter;
10位40MHz流水线模数转换器的设计
18.
Research and Design of 12bit 50Msps Pipelined A/D Converter;
12位50Msps流水线A/D转换器的研究与设计