1.
Design and implementation of a full parallel LDPC decoder
LDPC码全并行译码器的设计与实现
2.
An area-efficient parallel BCH decoder supporting foresighted error search
一种支持预搜索的面积紧凑型BCH并行译码电路
3.
Design of decoder for LDPC codes used in CDTTB standard
中国数字地面电视标准中LDPC码的半并行译码结构设计
4.
Parallel complementary decoding based on OSD and Chase
OSD和Chase的并行互补译码
5.
Parallel Maximum Likelihood Decoding Algorithm for RM Codes
RM码的一种并行最大似然译码算法
6.
Decoding Structure of Turbo Code Based on Parallel Prediction Control
基于并行预测控制的Turbo码译码结构
7.
The CODEC can be used to carry on coding transmission and decoding reception in parallel with code error detection and bit synchronized signal recovering.
该编译码器能进行并行发送编码和接收译码,并带有误码检测和位同步提取的功能。
8.
Design and Implementation of Hign Throughput Parallel Turbo Decoder;
高速并行Turbo译码器的设计与实现
9.
FPGA Implementation of a Novel Parallel Turbo Encoder/Decoder;
一种新型并行Turbo编译码器的FPGA实现
10.
Design and Implementation of Configurable Parallet BCH Decoder
可配置并行BCH译码器的设计与实现
11.
Design and Realization of Improved All-parallel Viterbi Decoder
改进型全并行Viterbi译码器设计与实现
12.
High-Speed Parallel BCH Decoder Circuit in VLSI
高速并行BCH译码器的VLSI设计
13.
Superposition feedback decoding algorithm for parallel concatenated block code based on correlation operation
并行级联分组码基于相关运算的叠加反馈译码
14.
A New Iterative Decoding Algorithm of Parallel Concatenated Block Code
并行级联分组码的一种新的迭代译码算法
15.
Since this code has simple structure and is easy to be implemented in parallel, a rather high decoding speed might thus be expected.
这种码的原理简单，易于并行实现，因而具有较高的译码速度。
16.
Research on Construction, Parallel Concatenation and Decoder Design of Low-Density Parity-Check Codes;
低密度奇偶校验码构造、并行级联与译码器设计的研究
17.
A Low Complexity Decoding Algorithm for Accumulated-Crossover Parallel-concatenated SPC Codes
累加交叉并行级联单奇偶校验码的低复杂度译码算法
18.
A cross-compiler runs on a host computer and produces object code for the target.
交叉编译器在主机上运行并且产生目标机的目标代码。