1.
DRDRAM Direct RAMBUS DRAM
直接内存总线DRAM
2.
BBL Back-side Bus Logic. Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
后端总线逻辑。访问内部统一二级处理器缓存的后端总线接口逻辑。
3.
The address bus specifies the memory locations (addresses) for the data transfers.
地址总线为数据传输指明内存位置（地址）。
4.
The actual address that is placed on the address bus when accessing a memory location or register.
当访问内存位置或寄存器时，在地址总线上的真实的地址。
5.
storage-out bus
输出总线 -存储器的
6.
controller bus address register
控制器总线地址寄存器
7.
From the point of view of the device, say the floppy disk controller, it will see only the address space that its control registers are in (ISA), and not the system memory.
从设备的角度来看，比如说软盘控制器，它只能看到在ISA总线上的控制寄存器而不是系统内存。
8.
First-generation PentiumⅡ systems with internal clock speeds up to 333MHz have an external memory bus speed of 66 MHz.
内部时钟速度达333MHz的第一代奔腾系统拥有速度为66MHz的外部存储器总线。
9.
Looking for disks on the same storage bus as the system disk...
正在系统盘所在的存储总线上寻找盘...
10.
Design of VXIbus Scan A/D Module with Large Capacity Memony;
VXI总线大存储容量扫描A/D模块研制
11.
Fieldbus System Design of Cigarette Storage Transmission Equipment;
卷烟储存输送设备现场总线系统设计
12.
High Speed Rate SDH Signal Storage System Based on PCI Express Bus
基于PCI-E总线的高速SDH信号存储系统
13.
Storage Design of Digital Storage Oscilloscope Basing on I~2C Bus
基于I~2C总线的数字示波器存储设计
14.
This stage makes heavy use of the video memory and the video memory bus.
这个过程中对显存和显存总线的负担比较大。
15.
Information is transmitted to and from registers via buses.
信息是通过总线输入寄存器或由寄存器输出的。
16.
Functionality in this area includes bus interface circuitry and a level2 cache.
本区域的功能包括总线接口线路和二级缓存。
17.
Storage~~Displays the amount of memory available and in use.
存储~~显示可用的和正在使用的内存总量。
18.
The total time during which an object or block exists.
某个目标程序或模块（在内存中）存在的总时间。