1.
A rapid block arithmetic coding algorithm in H.264
H.264中一种快速分组算术编码器算法
2.
An Optimized Architecture for the Arithmetic Encoder of JPEG2000
优化的JPEG2000算术编码器结构
3.
Novel optimized implementation of CABAC hardware encoder
CABAC算术编码器硬件优化实现
4.
Analysis of Static Image Compression Algorithm Based on the Improvement of QM Arithmetic Encoder
基于QM算术编码器改进的静态图像压缩算法
5.
Research on the Architecture of JPEG2000 and the Hardware Implementation of the MQ Coder in EBCOT;
JPEG2000系统架构研究及EBCOT中算术编码器的硬件实现
6.
Research and Design of the Context-Based Arithmetic Coding;
基于上下文的算术编码器的研究与设计
7.
Study and Design of Arithmetic Encoder for JPEG2000;
基于JPEG2000二进制算术编码器的研究与设计
8.
A Novel Arithmetic Coder for Bayer Pattern Images Compression
一种用于贝尔模板图像压缩的算术编码器
9.
FPGA implementation of adaptive arithmetic coder in H.264
H.264中自适应二进制算术编码器的FPGA实现
10.
Research and Implementation of the Adaptive Arithmetic Codec of JPEG2000;
基于JPEG2000的自适应算术编解码器的研究与实现
11.
Study on Video Codec Computation Efficiency Optimization Techniques of DSP Platform
DSP上视频编码器的计算效率优化技术研究
12.
coded form of arithmetic data
算术型数据编码形式
13.
FPGA Implementation of Arithmetic Coding in JPEG2000;
JPEG2000中算术编码的FPGA实现
14.
Research on Fast Algorithms in H.264 Video Coding and Error Detection of Arithmetic Codes;
H.264视频编码快速算法与算术编码检错研究
15.
Optimization of H.264 Video Coding Algorithm and Data Memory Organization for Decoder;
H.264编码算法与解码器存储结构优化
16.
In low bits-rate Vedio coding, all-zero block determination is a common technique to reduce the computational complexity of the encoder.
在低比特率视频压缩编码中,全零块的检测是一种常用的技术,用来减少编码器的计算复杂性。
17.
A High Performance Encoding Technology with Twitter-interference Elimination Based on FPGA
基于FPGA的抗编码器抖动干扰的高精度编码技术
18.
FPGA-based High-Voltage Inverter Pulse Signal Encoding Algorithm
基于FPGA的高压变频器脉冲信号编码技术的算法实现