1) I-cache
指令cache分析
1.
8e,chooses the extra reduction steps(ERs)in Montgomery Modular Multiplication Algorithm during the entire execution of RSA as the breakthrough entry,bases on the theoretical foundation that the ERs will be changed as the difference of the secret key bits,prefers to use I-cache analysis as our tool to detect the occurrences of ERs,and finally recovers the original key.
8e实现的RSA密码系统解密/签名执行过程为攻击对象,以RSA密码实现过程中利用的蒙哥马利模乘算法中的额外约简步骤为突破点,以随着密钥位的不同而会产生不同的约简步骤为理论基础,将指令Cache分析作为检测额外约简步骤发生的工具进行密码分析,最终恢复原始密钥,从而证明指令cache分析,对成功实施RSA密码攻击的可行性。
2) instruction cache
指令Cache
1.
To improve the operating efficiency of general micro processors,the architecture and design method of instruction cache are investigated.
为提高通用微处理器的执行效率,研究了高性能指令Cache的体系结构和设计方法。
2.
Most modern microprocessors employ on-chip caches to bridge the enormous speed disparities between the main memory and central processing unit (CPU), but these caches consume a significant fraction of total energy dissipation, especially the power dissipated by instruction cache itself is often a significant part of the power dissipated by the entire on-chip caches.
现代微处理器大多采用片上Cache来缓解主存储器与中央处理器(CPU)之间速度的巨大差异,但Cache也成为处理器功耗的主要来源,尤其是其中大部分功耗来自于指令Cache。
3.
Instruction prefetching is an effective mechanism to reduce the instruction cache miss rate.
指令预取技术能够有效地降低指令Cache的访问失效率,提高微处理器的取指令能力,进而提高微处理器的性能。
3) instruction cache design
指令Cache设计
1.
This paper analyzes the traditional instruction prefetch technologies,studies a new instruction prefetch technology based on the communications between compilers and processors with the Explicitly Parallel Instruction Computing architecture, and gives a L1 instruction cache design scheme supporting several technologies.
本文分析了传统的指令预取技术,并结合显性指令并行计算(EPIC)体系结构,研究了基于编译器与处理器通信的新的指令预取技术,提出了一种支持多种预取技术的L1指令Cache设计方案。
5) Cache Analysis
cache分析
6) Cache behavior analysis
Cache行为分析
补充资料：指令
指定计算机的操作和操作数或操作数地址的一组字符代码。由操作码和地址码组成。可被中央处理机理解和执行。操作码规定计算机操作的性质，地址码指出操作数所在地址和操作结果要送往的地址。参见“指令系统”。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条