1) Heterogeneous Multi-Core
多核异构
2) heterogeneous multi-core
异构多核
1.
This paper is to propose a design solution for heterogeneous multi-core architecture according to a kind of high-performance computing.
本文提出了一种针对高性能运算的异构多核结构设计方案。
2.
Many-core processor Characterized by heterogeneous multi-core architecture has become the mainstream of the development of processor technology direction,and how to implement a high efficient and available MPI on the many-core processor also will gradually become a research hotspot.
以异构多核为特征的众核处理器已成为处理器技术的主流发展方向,如何在众核上实现高效、可用的MPI将逐渐成为一个研究热点。
3.
Through the relationships among processor cores, instruction sets (ISA) and threads, this model is able to dynamically assign a thread to a configurable processor core with partially instruction extension in heterogeneous multi-core architecture, which can speed up the performance with less area increasing than full instruction extension SMP architecture, and simplify the programming model.
本文针对基于可配置处理器的异构多核结构,提出一种新的线程级动态调度模型。
3) Isomerous Muti-Core SoC
异构多核SoC
4) Heterogeneous multi-core processor
异构多核处理器
1.
Task scheduling algorithm for heterogeneous multi-core processor
异构多核处理器的任务调度算法
2.
Recently, heterogeneous multi-core processor, which consists of "the main processor & synergistic processor", has been developed rapidily, and drawn more attentions because it improves performance greatly in multimedia processing.
近年来,异构多核处理器,即“主核心+协处理器”发展迅速,对多媒体处理的能力大大增强,受到越来越多的重视。
3.
It is challenging to design a memory sub-system to suit to YHFT64-3,a heterogeneous multi-core processor with 18 float function units.
异构多核处理器可结合多种处理器体系结构的优势,既保留传统通用体系结构的灵活性,又拥有大量计算资源,可提供更高的峰值计算性能。
5) heterogeneous multi-core architecture
异构多核体系结构
1.
This paper designes in the environment of the heterogeneous multi-core architecture of reconfigurable Computing,using the C/C++ function pointer,with which everyone is familiar,and according to the results of hardware and software defragmentation,programmers accomplished the dynamic connection of the software or hardware function.
面向微处理器和可编程器件加速器的混合异构多核体系结构的可重构计算环境,采用程序员熟悉的函数描述格式,在运行时根据软硬件划分的结果,动态实现到软件函数实体代码或者硬件函数实现电路的连接。
6) Heterogeneous dual-core
异构双核
1.
The research objects in this paper including two self-developed embedded processors(CK520, SPOCK), and heterogeneous dual-core SoC(GEM-SOC) whic.
本文结合自主研发的两款嵌入式处理器(CK520，SPOCK)以及集成这两款处理器的异构双核SoC(GEM-SOC)，从高密度指令集、代码压缩方法以及代码解码器的实现方式三个方面开展了研究工作： 1)高密度指令集 以Thumb和MIPS16指令集为代表，讨论了双模式高密度指令集的工作方式以及优缺点；以CK-core指令集为代表，从编程模型、指令类型、指令编码以及寻址方式等方面分析了单模式高密度指令集如何在代码密度和处理器性能之间作折衷；并以Powerstone基准测试集为基础，ARM940T和CK520为例，对比分析了Thumb/ARM和CK-core指令集的代码密度和处理器性能，实验结果显示：在使用相同的编译器条件下，与32位ARM指令集相比，CK520在牺牲17％处理器性能的前提下降低了38％的代码量；与16位Thumb指令集相比，CK520指令集不仅能够降低9。
补充资料：磷酸核酮3-差向异构酶
分子式：
CAS号：
性质：又称磷酸核酮3-差向异构酶，核酮-5-磷酸-3-差向酶。它广泛分布在生物体内，属于异构酶类(isomerases)中的差向异构酶(epimerases)之一。EC5.1.3.1.。它所催化的反应如下：为此它的系统命名是：D-核酮糖-5-磷酸3-差向异构酶。在异构体转化过程中存在有烯醇式中间物。该酶在磷酸戊糖途径(又称磷酸己糖支路)中对核糖的生物合成，戊糖间相互转化，和使磷酸戊糖途径与糖酵解过程有机衔接上具有重要生物化学意义。
CAS号：
性质：又称磷酸核酮3-差向异构酶，核酮-5-磷酸-3-差向酶。它广泛分布在生物体内，属于异构酶类(isomerases)中的差向异构酶(epimerases)之一。EC5.1.3.1.。它所催化的反应如下：为此它的系统命名是：D-核酮糖-5-磷酸3-差向异构酶。在异构体转化过程中存在有烯醇式中间物。该酶在磷酸戊糖途径(又称磷酸己糖支路)中对核糖的生物合成，戊糖间相互转化，和使磷酸戊糖途径与糖酵解过程有机衔接上具有重要生物化学意义。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条