1) attack-verify platform
攻击验证平台
1.
By analyzing a variety of practical botnet, this paper utilizes the spread and control mechanisms of typical botnet to implement a large-scale network attack-verify platform whose framework is the controllable botnet.
本课题开展对可控僵尸网络的研究,并以此形成大规模网络的攻击验证平台,为网络攻防的研究打下坚实的基础。
3) attack platform
攻击平台
1.
The design and implement of a network auto-attack platform;
一种网络自动攻击平台的设计与实现
4) testbench
验证平台
1.
Research and Application of an Efficient Testbench Based on Verilog;
基于VERILOG的一种高效验证平台的研究及应用
2.
Since systemC language was good at behavior description,design method of behavior models and testbenchs using systemC instead of HDL in IP soft core design were introduced in this paper.
在IP软核的设计过程中,可以利用SystemC行为模型描述特点代替传统HDL语言,建立行为模型和验证平台。
3.
Based on these research,a relevant testbench design is proposed.
分析了IP核设计过程中功能验证的重要性,研究了CIU96B IP核设计,在此基础上提出了一个相应的验证平台设计,仿真显示该验证平台结构的实现了对该IP核的验证,有效地促进了该IP核的设计。
5) verification platform
验证平台
1.
Construction of verification platform based on SD/MMC controller;
基于RVM SD/MMC卡控制器验证平台的搭建
2.
Design and Application of Microprocessor Hardware Verification Platform;
微处理器硬件验证平台的设计与应用
3.
Design of FPGA verification platform of 32 bits RISC microprocessor;
32位RISC微处理器FPGA验证平台设计与实现
6) input validation attacks
输入验证攻击
补充资料：DVT 设计验证(Design Verification Testing)
以测试产品的功能性为主，通常还包含Debug。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条