1) MF MicroOps Fusion
微指令合并
2) instruction folding
指令合并
1.
In this paper, the technology of instruction folding in Java processor is studied on the basis of analyzing the Java virtual machine and Java bytecodes.
文中在分析Ｊａｖａ 虚拟机及字节码特性基础上，研究了Ｊａｖａ 处理器中的指令合并技术。
3) parallel instruction
并行指令
1.
The hierarchical memory management of BF535 is analyzed, and the memory in different region is described, According to the L1 and L2 RAM of the DSP, parallel instruction and FFT operation is evaluated.
其次,针对该DSP的L1、L2,进行了并行指令和FFT运算的性能评测。
4) merge instruction
归并指令
5) instruction parallel
指令并行
1.
Based on the in-depth research of FT-C55LP’s characteristics of instruction sets and instruction parallel, I have a comprehensive and detailed analysis of the instruction sets of FT-C55LP, and put forward a design plan of decoding controlling unit, which is divided into three modules: parallel instruction splitting, single instruction decoding, and decoded signal incorporating.
作者对FT-C55LP的指令集进行全面而详细的分析,在深入研究指令集特点和指令并行特征的基础上,给出了译码控制单元的设计方案。
6) Microinstruction
[,maikrəuin'strʌkʃən]
微指令
1.
A simplified CPU model consists of ALU,PC,IR,DR,AR and Instruction Decoder,which play an important role in the exexution of microinstructions,while several microinstructions make an instruction.
简化CPU模型中主要包括算逻单元ALU,程序计数器PC,指令寄存器IR,数据寄存器DR,地址寄存器AR和指令译码器,这些部件对于微指令的执行起着至关重要的作用,而微指令流的顺序执行又导致了指令的执行,因此微指令如何构成以及如何执行就成了程序运行的硬件基础,从这个意义上说,微指令的分析与设计对于理解整个CPU的结构和功能至关重要。
2.
Firstly, the instruction testing is decompounded into microinstruction sequencing level and micro.
首先 ,依据指令的表示模型 ,将指令测试分成微指令序列和微指令执行两个测试层次 ,提出了一个基于微指令覆盖的最小指令集测试算法 ,只需检测指令集的一个子集就能达到指令测试的目的 。
补充资料：微指
1.见"微旨"。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条