In this paper,the quantitative conception of "higher frequency DDS signal" is defined;the Non-ideal characteristics of DAC is analyzed,especially the performance of DAC s setting time;the correlation of slew time and setting time is proposed;a simplified trapeziform .

Analysis and optimization of settling time and phase margin of two stages operational amplifier;

The MATLAB optimization program can find the optimal damping factor and natural frequency that makes the settling time of OTA in minimum quickly.

The accurate measure of the setup time of high-speed ADC-driven circuit

An approach how to check the setup time and the hold time of the integrated circuit port signal with the aid of the timing check system in the integrated circuit timing verification stage is introduced in this article.

Six clock design measures for the field programmable gate array(FPGA) are described in this paper which preset a credible clock design according to the setup time,hold time and synchronous principle.

Considering the influences of some uncertain error sources under practical engineering condition, it is showed that both rotating time and stopping time of the INS have effect on system acceleration error observations during the calibration process, and may have further effect on inertial instruments error computation.