1) iterative sequential circuit
累接时序电路
2) iterative circuit
累接电路
3) Sequence circuit
时序电路
1.
Sequence circuit test patterns always have redundancy.
时序电路测试生成算法产生的向量存在冗余。
2.
The paper introduces a simple and direct method of simplifying logic function by making use of Karnaugh map in designing sequence circuit.
介绍了在时序电路设计中应用卡诺图进行逻辑函数化简时的一种简捷方法，按本方法化简设计出的电路可以满足所用触发器和门电路数目最少以及触发器和门电路输入端数目最少的“最简”要求。
3.
And applies this method to the sequence circuit.
介绍了常用于组合逻辑电路故障检测的特征分析法,并将这种方法应用于时序电路。
4) Sequential circuit
时序电路
1.
The start from introduction of the general characteristic formula of trigger,and explains the theory and methods on analyzing as synchronized sequential circuit.
从介绍触发器广义特性方程入手 ,阐述了应用它分析异步时序电路的原理和方法 ,并举例说明了应
2.
During the design process of low voltage equipments using flow chart and state matrix, the distributing control functions using Karnaugh map can satisfy the demand for the design of sequential circuits with/without intermediate states.
用流图法和状态矩阵设计低压电器电路时 ,卡诺图法分配控制函数能较好满足无过渡态和有过渡态的时序电路设计 。
3.
Flow chart and state matrix can be used to identify and design sequential circuits in the basic low voltage equipment.
基本低压电器时序电路可用流图和状态矩阵来进行规范系统识别和设计 。
5) sequential circuits
时序电路
1.
Initialization for synchronous sequential circuits based on particle swarm optimization algorithm;
基于粒子群算法的同步时序电路初始化
2.
Simulation method of solving stable state in the gate level sequential circuits;
求解门级时序电路稳定状态的仿真方法
3.
Research on Automatic Test Generation of Sequential Circuits Based on Ant Algorithm;
基于蚂蚁算法的时序电路测试生成研究
6) sequential logic circuit
时序电路
1.
The Implementation of sequential logic circuit with GA in EH;
演化硬件技术中时序电路的遗传算法实现
补充资料：时序女神
时序女神(horae)：宙斯和忒弥斯诸女，
欧诺弥亚(eunomia）秩序女神
狄刻(dike)公正女神
厄瑞涅(eirene）和平女神.
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条