A realizable equivalent γdn model for RLC interconnect driving point admittance is proposed in this paper.

A close ended equivalent π model for RLC interconnect tree to estimate the driving point admittance is proposed.

The old gatedelay models utilizing the theory that equivalent output driving point admittance formulation isequal can’t combine with equivalent capacitance formulation very well, which results in the toopessimistic or optimistic gate delay.

A method of cross-point admittance based on ambient excitation to identify large engineering structures modal parameters was reported in this paper.

This paper constructs a stable RLC interconnect π model based on the first three moments of the node admittance,and discusses its application to interconnect delay and logic gate delay estimation.