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1)  bucket-brigade delay line
斗链式延迟线
2)  bucket-brigade delay line
戽斗链延迟线
3)  delayed-line network chain
延迟线网络链
4)  delay chain
延迟链
1.
Frequency measurement method based on delay chain;
基于延迟链的频率测量方法
2.
A factorjzation algorithm for linear-phase paraunitary filter banks with optimized delay chains;
一种优化延迟链结构的线性相位准正交数字滤波器组的算法
3.
It collects output signals from the delay chain at the same time in order to enhance the randomness of the output sequence.
本文分析和实现了一种基于FPGA的真随机数发生器,采用对延迟链各级输出同时采样的方法来增加输出序列的随机性。
5)  link delay
链路延迟
1.
Modeling internet link delay based on measurement
测量的Intnernet链路延迟建模
2.
By dealing with the raw giant data samples authorized by CAIDA,we obtain one-way link delay.
通过对CAIDA机构授权的原始海量样本数据处理得到单向链路延迟,在此基础上计算了路径上最大的链路延迟对端到端延迟的比例以及路径上链路个数分布,基于此定义了支配延迟。
3.
Furthermore,a research on the relationship between the traveling diameter and the traveling time from the whole and local data samples supposed that link delay was the leading cause for the great variance of the traveling time,and a revising algorithm was proposed to process the raw data samples to .
在此基础上对Internet的访问直径与访问时间之间的关系从整体和局部样本进行研究,认为链路延迟是导致相近的访问直径其访问时间相差较大的主要原因,并提出修正算法从样本数据得到链路延迟。
6)  delay line
延迟链
1.
Traditional DLL design using only one layer of delay line faces the contradiction between the number of delay units and precision,resulting in huge amount of logic resource and chip area.
新设计创新性地采用多层次延迟链的结构,分粗、细、微调3级逐次进行延迟补偿。
2.
Experiments show that the proposed method has solved the problem of the traditional multi-phase sampling approach,to which phase shift resolution is decreased with the frequency increasing,so that the fine resolution can be obtained by limiting delay lines and no increase of counting clocks.
该方法在现场可编程门阵列(FPGA)中实现了脉冲计数法、多相采样法和延迟链法的结合。
补充资料:延迟线
在电路中将电信号延迟一定时间再输出的器件。对模拟信号一般用电感和电容组成或直接用同轴电缆和螺旋线;数字信号还用电荷耦合器件或声表面波器件。延迟时间约为10-9~10-5秒。广泛用于雷达、通信、计算机、彩色电视及测量仪器(如示波器)中。
说明:补充资料仅用于学习参考,请勿用于其它任何用途。
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