Rectangle-packing-based floorplanning algorithms for system-on-a-chip design;

The Boundary Constraints of Floorplanning Based on Single-Sequence;

Simulation annealing accelerating in VLSI floorplanning

Application study on the drawing flow in city planning based on spatial database of GIS;

The research on "integrating high level synthesis and floorplan" is a very important part in the research on electronic design automation.

In practice of floorplan/placement of very large scale integration(VLSI) physical design,it is very critical to place some modules along the boundaries of the chip so that connections between inputs and outputs and among units in hierarchical design mode are shortened.

Creating or deleting objects graphplan based on conditional effects;

Plan Synthesis and Decomposition in Graphplan Framework;

The Research on Goal-Directed Temporal Graphplan Algorithm;