This paper firstly analyses the methods of weighted pseudo random pattern generation and dual-speed LFSR,then proposes an improved DS-LFSR structure combined with weighted pattern testing.

The research of multi - fault test generation for combinational logic circuits;

Binary decision diagram method for test generation of digital circuits;

Neural networks based test generation algorithm for combinational logic circuits;

A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.

A path delay fault testing generation algorithm based on Boolean difference for digital circuits is proposed because the testing generation for path delay fault in digital circuits is more difficult.

In order to obtain better failure coverage and testing set of digital circuit and reduce the reverse backtracking,many bionics algorithms are applied to testing generation of circuit.

In order to solve the hard problem of testing for synchronous sequential circuits, improve the test generation efficiency of sequential circuits, this dissertation studies the algorithms of test pattern generation for sequential circuits.

As the traditional GM(1,1) model does not reflect the importance of the new information,this paper presented the concept of weighting accumulated generating operation and made a research on its properties including monotonic property,grey exponent law and convexity.