1) Loop Delay
环路延时
1.
Based on digital peak voltage controlled Buck converter, the presence of the loop delay in digital controller of switchign DC-DC converter was investigated, and proposed improved digital peak voltage control by a way to eliminate one-switching-cycle-delay.
研究数字控制环路延时对开关变换器瞬态性能的影响,提出克服环路延时影响的简单实用算法。
2) DLL Delay-Locked Loop
延时锁定循环电路
3) time delay for short-circuit
短路延时
4) time delay circuit
延时电路
1.
Three familiar problems of using VHDL hardware description language to design FPGA under the MAX plus II development platform are discussed in detail,the grade duty ratio frequency dividing circuit,the time delay circuit,the bilateral circuit.
详细讨论了在MAX plus II开发平台下使用VHDL硬件描述语言设计现场可编程门阵列(FP-GA)时常见的三个问题:等占空比分频电路、延时任意量的延时电路、双向电路。
2.
How to use the CMOS buffer to make up the capacitance charge-discharge type long time delay circuits is studied.
对采用CMOS缓冲器组成电容充放电式长时间延时电路进行了研究。
5) multi-channel time-delay
多路延时
6) time-delay circuit
时延电路
1.
Two-channel high-voltage trigger generator using artificial transmission line as time-delay circuit;
将多路高电压触发器的运行模式从"先延时后触发"改变为"先触发后延时",并用人工传输线代替集成电路芯片构成时延电路,这大大提高了多路高电压触发器的抗电磁干扰能力。
补充资料：安培环路定律(见磁场强度)
安培环路定律(见磁场强度)
Ampere's circuital law
A rlpe{h口。)11L一dingILJ安培环路定律(Amp之re’5 CirC。ital law)见磁场强度。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条