A frame synchronization algorithm based on IEEE802.11a WLAN standard;

Maximum A Posteriori-based frame synchronization algorithm;

Design and implementation of an FPGA-based PCM frame synchronization detection and alarm system;

We combine the error-tolerant technology with no error-tolerant technology to carry out the detection of the frame synchronization code.

Design and implementation of the frame synchronizer with adaptive phase based on synchronization state machine;

A new frame synchronizer for turbo code based on the fusion of two kinds of information is proposed in this paper.

A frame synchronizer with recognizer and discriminator is described, which consists mainlyof a type 8951 singlechip computer, a type 8254 programmable counter and a GAL chip.

The FPGA Design of AOS Frame Synchronous Transmitter Based on PCI Bus;

But in the hardware design phase,there was few I/O pin can be used,so don t have the frame synchronous signal in communication,only the clock control signal and the serial data signal were used in receiving the GPS serial data frame.

Based on the analysis to PCM30/32 basic group s frame structure and the structure and function of frame synchronous circuit,the chapter has designed with VHDL the frame synchronous circuit with up-down method of modern electronic designing by using EDA simunation software Modelsim SE 5.

Study and Implementation of Frame Synchronizer Based on FPGA;

Design and Implement of Frame Synchronizer;