1) pre-amplifier-latch comparator
预运放-锁存比较器
2) preampilifer-latch comparator
预放大-锁存比较器
3) Preamplifier-latch comparator
预放大锁存比较器
1.
Based on the research and analysis of system structure of 10-bit 100MSPS Pipelined CMOS ADC, according to the system performance, the specifications of sub_ADC is obtained, while the sub_ADC including the preamplifier-latch comparator, the reference ladder resistance and the clock-control encode circuits are d.
基于对10-bit 100MSPS Pipelined CMOS ADC系统结构的分析研究,结合系统性能确定了子ADC的指标要求,详细讨论并设计了子ADC单元模块的设计,包括预放大锁存比较器,参考电阻串和时钟控制编码电路。
2.
To reduce power dissipation of a sigma-delta analog-to-digital converter,a new high-speed and low-power dissipation CMOS preamplifier-latch comparator,which is suitable for use in a sigma-delta analog-to-digital converter,was presented in CMOS 0.
18μm工艺,提出1种由参考电压产生电路、预放大器、锁存器以及用作输出采样器的动态锁存器组成的新型高速低功耗的CMOS预放大锁存比较器。
4) latch comparator
比较锁存放大器
5) latched comparator
锁存比较器
1.
Design of the fully differential high speed low voltage latched comparator
全差分高速低电压锁存比较器的设计
2.
This paper expounds a high-speed CMOS latched comparator with large gain suitable for △-∑ modulator.
本文设计了一款用于△-∑调制器的高增益高速CMOS锁存比较器。
6) bipolar latch comparator
双极锁存比较器
补充资料：运亡为存
1.犹言救亡图存。
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参考词条