1) receive/send timing
收发时序
2) timing closure
时序收敛
1.
A Method of Timing Closure Based on Crosstalk in Deep-Submicrometer Physical Design of SoC Chip;
深亚微米SOC芯片物理设计中基于串扰的时序收敛方法
2.
A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.
针对深亚微米工艺下版图设计中存在的时序收敛问题,提出了一种区域约束的版图设计方法。
3.
The Assignment Editor in Quartus II supports various constraints including timing closure.
基于Altera现场可编程门阵列的逻辑锁定设计方法可提高复杂系统设计时的效率,在设计整合时,能更好地继承各个模块的实现结果;约束编辑器提供了指导Quartus II软件对设计进行时序收敛的一种手段。
3) timing convergence
时序收敛
1.
Some methods of improving timing convergence are presented,and the design of butterfly unit in FFT processor is taken as an example to describe the application of STA to high speed and large scale FPGA design.
针对时序不满足的情况,提出了几种常用的促进时序收敛的方法。
4) time-ordered contraction
时序收缩
5) receiving and transferring program
收发程序
6) time-sharing receive and transmit(TSRT)
分时收发
补充资料：收发
1.收进和发出。 2.职务名。掌管文件﹑信函等的收进和发出。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条