3) VHDL
硬件描述语言(VHDL)
4) HDL
硬件描述语言
1.
Implementation of Viterbi Decoding With Verilog HDL;
用Verilog硬件描述语言实现Viterbi译码
2.
Building of HDL MP3 Decoder′s Test Bench and IP Core Reuse;
基于硬件描述语言的MP3解码器仿真平台的搭建以及IP Core的重用
3.
Designing Digital-Calculagraph By Verilog HDL;
用Verilog硬件描述语言设计数字计时器
5) verilog HDL
Verilog硬件描述语言
1.
This article analyzes the theory of power consumption in digital circuit, writes a power consumption model in gate level using Verilog HDL according to the theory, and applies this model into three different structured adders.
对数字电路中的功耗产生机理进行了分析 ,根据此原理 ,利用 Verilog硬件描述语言编写了一个门级功耗模型 ,并将他应用到 3种不同结构的加法器中 ,分别测量其功耗 ,分析了功耗大小不同的原因。
2.
Then, the thesis gives design details of all the major modules of the JPEG decoder which is implemented using Verilog HDL also with the simulation waveforms and the implementing results after the JPEG decoding algorithm was studied deeply.
采用了Verilog硬件描述语言对JPEG基本模式硬件解码器的各主要模块进行设计实现,并给出了功能仿真波形图及测试结果。
3.
The endpoints controller is designed in Verilog HDL for USB2.
采用Verilog硬件描述语言设计了用于USB2。
6) hardware description language
硬件描述语言
1.
Digital clock design based on the hardware description language(VHDL);
基于硬件描述语言(VHDL)的数字时钟设计
2.
All the functions were programmed with the hardware description language VHDL, key code of the program,and were dow nloaded into the object chid XC3S500E,Spartan3E Series,Xilinx.
对各个模块功能加以说明,通过硬件描述语言VHDL编程实现,并给出部分主要程序代码,Spartan3E系列的XC3S500E目标芯片上通过调试。
3.
The digital part of LCD controller was modeled by Verilog hardware description language.
根据“自顶向下”的设计思想 ,将系统进行层次化功能划分 ,并用Verilog硬件描述语言对各模块进行了RTL实现 。
补充资料：BASIC语言(见程序设计语言)
BASIC语言(见程序设计语言)
BASIC
吕AS{CBASICyLJy〔1下〕语言(BASIC)见程序设计语言。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条