1) SoC bus
系统芯片总线
1.
SoC bus based power analysis technique is appropriate for system level power estimation.
Wishbone总线具有简单、灵活、免费等特点,是具有较强竞争力的系统芯片总线(SoC Bus)标准之一。
2) bus chip
总线芯片
3) Wishbone system-on-chip(SOC) architecture
Wishbone片上系统总线
4) SoC
系统芯片
1.
Design of Low Cost-Electronic Compass Based on SoC;
基于系统芯片(SoC)的低成本电子罗盘的设计
2.
Design of Hardware Verification Platform for Embedded Reconfigurable SoC;
嵌入式可重构系统芯片的硬件验证平台设计
3.
A Test Schedule Model and Corresponding Algorithm for SoCs;
系统芯片测试调度模型及其调度算法
5) system-on-a-chip
系统芯片
1.
The Research on Test Data Compression of System-on-a-Chip (SoC);
系统芯片SoC测试数据压缩方法研究
2.
Many novel testing structures for system-on-a-chip are proposed for decreasing testing cost and facilitating test reuse.
为了降低系统芯片测试成本,需复用IP的测试电路和测试矢量,过去几年已经涌现了许多新型测试结构。
3.
With rapid growth in integration and complexity of System-on-a-Chip (SoC), volume of test data required in large-scale integrated circuits test increases accordingly.
随着系统芯片(SoC)集成度和复杂性的迅速提高,大规模集成电路测试需要的测试数据相应增加,而传统自动测试设备(ATE)的存储量、工作频率以及带宽的有限性,使得SoC测试面临着测试时间过长、测试难度和测试成本急剧增加等诸多问题。
6) system-on-chip
系统芯片
1.
Research on the Design Optimization Techniques for System-On-Chip Testing;
面向系统芯片测试的设计优化技术研究
2.
Setting Constraints and Logic Synthesis for Novel PKUnity System-on-Chip;
面向新型北大众志系统芯片的约束设置与逻辑综合
3.
With the development of VLSI technology and increasing complexity of System-on-Chip applications,on-chip communication architecture design encounters some problems,such as throughput,power,signal integrity,latency and clock synchronization,Network-on-Chip(NoC)was introduced.
半导体技术的发展以及系统芯片应用复杂度的不断增长,使得片上互连结构的吞吐量、功耗、信号完整性、延迟以及时钟同步等问题更加复杂,出现了以片上网络为核心的通信结构。
补充资料：飞机数据总线(见机载信息综合处理系统)
飞机数据总线(见机载信息综合处理系统)
aircraft data bus
fei份州兰碧叩灿“飞机数据忌玫咬alrerar:aa:。。u、)机载信息综合处理系统。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条