Two important techniques to reduce leakage power in caches are sleep cache and drowsy cache in which the cache lines unused recently can be put into low-power mode.

This paper provides a cache leakage power estimation model based on statistics.

Solutions to some technological difficulties such as leakage power opt.

The leakage power issue is challenging high-performance microprocessor design, especially as feature size shrinks.

Based on the “amplifying” idea,simple circuits for measuring the gate delay,dynamic power,leakage power,and their variations for a 90nm process are designed.

However, few researches in the literature have focused on reducing the leakage power in PIL1.

In this paper,we propose an on-demand mechanism for data cache leakage power management,which manages data cache activities according to the demand of memory accessing instructions.

A design methodology of leakage power optimization is introduced and some practica.

As a result, leakage power will dominate total power dissipation soon.

To carry out the attacks of RSA CMOS(Complementary Metal Oxide Semiconductor) chips,the paper has investigated the theory of the differential power analysis based on the power consumption of cipher chip.

The paper calculates theoretically the influence of different kind of PI with different thickness on the static current of LCD, then compares in practice the influence of KPI-300B and SE-2170 on the static current, and two dilution (NMP from Germany and NIS-SAN PI special dilution 21) mixed with PI upon the static current of LCD.