1) Verilog HDL
VerilogHDL语言
2) VerilogHDL language
VerilogHDL语言
1.
The UART core function is described using VerilogHDL language and optimized in the RTL code.
该UART核采用VerilogHDL语言描述其功能,对RTL级实现优化,解决了多时钟、亚稳态和毛刺等问题。
3) VerilogHDL hardware description language
VerilogHDL硬件描述语言
4) Verilog HDL
VerilogHDL
1.
Two Special Data Types in Verilog HDL and Evaluation of the Variables;
VerilogHDL语言中的特殊数据类型及其赋值
2.
A Verilog HDL- based Pipelining Design Method and its Application;
基于VerilogHDL的流水线的设计方法及应用
3.
This paper mainly introduces the principle of equal observations for frequency,which has the merit of keeping high degree of accuracy for frequency measurement in entire test wave band;meanwhile,on base of this principle,adopts Verilog HDL to design high speed integrated circuit for equal observations of frequency,and uses EDA development tool QUARTUSⅡ3.
主要介绍了等精度频率测量原理,该原理具有在整个测试频段内保持高精度频率测量的优点;同时在该原理基础上,采用了VerilogHDL语言设计了高速的等精度测频模块,并且利用EDA开发平台QUARTUSⅡ3。
5) verilogHDL simulation
verilogHDL仿真
6) VerilogHDL code
VerilogHDL代码
补充资料：BASIC语言(见程序设计语言)
BASIC语言(见程序设计语言)
BASIC
吕AS{CBASICyLJy〔1下〕语言(BASIC)见程序设计语言。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条