1) source coupled logic
源极耦合逻辑
1.
The source coupled logic (SCL) D flip-flops are adapted to reduce the switching noise and power consumption, also for high frequency operation.
描述了一个应用于高集成度2 GHz频率综合器的预分频电路的设计,预分频电路中D触发器采用了源极耦合逻辑电路结构,可以提高电路工作频率,同时有效减小开关噪声和电路功耗。
2.
They are implemented with CMOS logic and source coupled logic(SCL).
具体电路由锁存器、选择器及分频器组成,以CM O S逻辑和源极耦合逻辑(SCL)实现。
2) SCL
源耦合逻辑
1.
In the higher frequency band, M/S DFF structured by CMOS SCL were used to divider; In the lower frequency band, DFF with self-latch function were used to implement High-Speed Low-Power Low-Jitter Dual Modulus Divider-by 32/33 Prescaler.
提出了一种新颖的分频器设计方案,在高频段采用改进的CMOS源耦合逻辑(SCL)结构的主从D-Latch进行分频;在低频段采用自锁存的D触发器进行分频,从而实现高速、低功耗、低噪声双模前置32/33分频器。
2.
A dual-modulus divide-by-32/33 prescaler has been implemented using source-coupled logic (SCL).
该文采用改进的CMOS源耦合逻辑(SCL)结构,设计了32 33分频的高速、低功耗双模前置分频器。
3) SCL circuit
源极耦合逻辑(SCL)电路
4) source coupled FET logic
源极耦合场效应管逻辑
1.
In order to meet with the requirements of high-speed,the source coupled FET logic (SCFL) is applied in all of the circuits.
为了适应高速度的要求,所有电路全都采用源极耦合场效应管逻辑来实现。
5) collector-coupled logic
集电极耦合逻辑
6) emitter coupled logic gate
射极耦合逻辑门
补充资料：发射极耦合逻辑集成电路
晶体管导通时工作在非饱和区的一种逻辑集成电路。有“或”和“或非”两种输出。可构成各种逻辑关系。特点为开关速度快，甚至达亚毫微秒，但功耗大，抗干扰力差。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条