Two novel types of low clock-swing TSPC flip-flops;

The design of low-swing clock low power double-edge-triggered flip-flop;

The scheme takes advantages of repeaters and low-swing differential-signaling circuits on driving long wires in different length,and optimally inserts them along the wire in order to decrease delay and power of interconnects.

The method is based on a digital PID(proportional-integral-derivative) controller and phase-locked loop,using the wobble clock read from the CD-R disk as the feedback signal.