1) loop statement
循环语句
1.
The ways of synthesis "loop statement", "if statement" and "case statement" are different under different VHDL timing and constraints.
根据这一含义,说明并实现了VHDL中循环语句的综合方法、条件语句和分支语句的综合方法,并实现了与循环有关的其它语句的综合。
2.
The synthesis of loop statement is very important in high level synthesis.
循环语句是高级综合中非常重要的语法现象[1] 。
3.
Here presented is a method to implement loop statement synthesis in RTL synthesi s,which extracts loop statements from behavior description in order to form loop statements list,then finish format discriminance and synthesize.
文中提出一种在RTL综合中实现循环语句综合的方法 。
2) for cyclic sentence
for循环语句
3) while cyclic sentence
while循环语句
4) repeat-until loop statement
Repeat-until循环语句
5) assignment statement loop
赋值语句循环
6) for clause
循环子句
补充资料：循环语句
实现重复计算和操作的语句。即解决循环问题的语句。许多高级语言中都有好几种循环语句。一般均设置一个退出或进入循环的条件来控制循环的次数。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条