In view of some characteristics of digital image,a new method of floating-point operation is implemented on a ordinary FPGA chip.

According to floating-point operation process, the floating-point operations are divided into three stages, namely, the pre-normalization stage, calculation stage and post-normalization stage.

The fixed-point multiplier-adder is used to implement floating-point operation,which is simulated and implemented on FPGA.

The design has been used in the IP software core design of 32 b complex floating point operation as a module,and acquire a g.

This paper analyzes the causes of error resulted from many ways, such as floating-point arithmetic, temperature, pressure measuring loop, choice of sampling cycle, so that the problems can be noticed.

To improve the floating-point arithmetic performance of Navigation Computer,and to meet the requirement of real-time performance of integrated navigation system,a navigation computer with floating-point auxiliary processor is proposed.

The hardware implementation is very difficult because of floating-point arithmetic disadvantage of complex computation and too much hardware resource consuming.

Step motor is a kind of flexible control equipment, on the other hand, DSP has high speed and floating operation capacity.

Implementation of float number operation on CPLD/FPGA chip by VHDL;