1)  DM642 CPLD
DM642 CPLD
2)  DM642
DM642
1.
Research about high-speed data tromsfer based on PCI interface of DM642;
基于DM642的PCI总线接口技术的高速数据传输研究
2.
Design of CMOS image capture system based on TMS320DM642;
基于TMS320DM642的CMOS图像采集系统的设计
3.
Implementation for Video Coding System of the H.264 Based on TMS320DM642;
基于TMS320DM642的H.264视频编解码系统实现
3)  CPLD
CPLD
1.
Design of electron coded lock by CPLD;
基于CPLD的电子密码锁设计
2.
Design of Hardware Architecture about Embedded Loom Control System Based on CPLD Expanding;
基于CPLD扩展的嵌入式织机控制系统硬件结构设计
3.
Application of CPLD Technique in Natural Gamma Well Logging Tool;
CPLD技术在自然伽马能谱测井仪中的应用
4)  complex programmable logic device
CPLD
1.
Design and Application of High Speed and High Accuracy Multi-channel Data Acquisition Controller Based on Complex Programmable Logic Device;
基于CPLD的多通道高速高精度数据采集控制器设计及应用
2.
Design of microcomputer-based fault line selection device for compensated distribution networks based on 80296 and complex programmable logic device;
基于80296和CPLD的补偿电网微机选线装置的设计
3.
0 is designed to transfer image data,and a complex programmable logic device is used to control the time sequences between them.
设计并实现了一种数字图像采集系统,系统采用CMOS芯片MCM20027采集图像,在CPLD的时序控制下,通过USB2。
5)  Complex programmable logic Device(CPLD)
CPLD
1.
The device makes use of the characteristics of complex programmable logic device(CPLD),such as high speed,agility and programmability,utilizes the way of "sampling synchronously,converting asynchronously",and achieves the controlling of A/D sampling and converting that needs strict schedule and logic.
该装置充分利用逻辑可编程器件(complex programmable logic device,CPLD)高速、灵活、可编程的特点,采用"同时采集,分时转换"的采样处理方式,实现了具有严格时序和逻辑要求的A/D采样转换控制。
2.
The control mainframe of the robot is composed of a Digital Signal Processor(DSP) and a Complex Programmable Logic Device(CPLD).
其控制主体采用DSP(数字信号处理器)结合CPLD(复杂可编程逻辑器件)。
3.
On the basis of Complex programmable logic device(CPLD) and digital programmable delay line,high-precision phased ultrasonic transmission in phased array ultrasonic systems is designed in this paper.
本文研制了基于复杂可编逻辑程器件(CPLD)和可编程数字延迟线(AD9501)的超声相控阵系统中的高精度相控发射系统。
6)  TMS320DM642
TMS320 DM642
1.
Design and Realization of Secondary BOOTLOADER for TMS320DM642 DSP;
TMS320 DM642 DSP二级引导程序的设计与实现
参考词条
补充资料:宇文士及(?-642年)
宇文士及(?-642年) 宇文士及(?-642年)   隋间官吏。字仁人,京兆长安(今陕西西安)人。文帝诏尚南阳公主,封尚辇奉御。后随唐太宗征讨有功,封新城县公,太宗以宗宝女妻之。后颇受宠而历任官职。辑有《妆台方》(一作《妆台记》),已佚。
说明:补充资料仅用于学习参考,请勿用于其它任何用途。