1) pipeline structure
流水线结构
1.
The advantage of high rate clock in the DVB system results in a higher decode speed in the Modified Euclidean algorithm block,optimization of the pipeline structure of the decoder and efficient reduction of the chip area.
在解码器的设计中充分利用了DVB系统提供的高倍率时钟,提高了核心算法模块的计算速度,优化了解码器的流水线结构,有效减小了芯片面积。
2.
Some optimization techniques such as 4-level pipeline structure and ROM data compression are used in the design.
利用FPGA芯片及D/A转换器,采用4级流水线结构和ROM数据压缩等优化技术,设计实现了一个频率、相位可调的正弦信号发生器,取得了较好的整体性能,得到了较理想的波形和较好的频谱。
3.
Considering both the speed and the complexity,this method uses three-stage pipeline structures based on Radix-4 algorithm by DIT.
该方法从运算速度和实现复杂度两方面综合考虑,采用基于按时间抽取的Radix-4算法的三级流水线结构,每级将乘法器的旋转因子输入端固定为常数值,而不是作为变量从ROM中读取,从而减少ROM的读取时间。
2) pipeline architecture
流水线结构
1.
To further increase the throughput the three stage pipeline architecture is adopted inside the processing element, so that every one bit result outputs at one clock cycle when the pipeline is filled.
提出了一种新型的线性脉动阵列结构用来实现基于Montgomery算法的并行模乘运算,对于n位模乘运算,需要2n+11个时钟周期完成,为了减少每一周期内的运算量,在处理单元内部实现了三级流水线结构,使得每一周期的串行运算量仅为一级全加器,同时,由于处理单元间只有局部互连,连线延迟很小,于是这种新结构脉动阵列模乘器能在很高的频率下工作。
2.
In this paper,an optimized single-symbol 3-stage pipeline architecture for AE is presented,which makes up the flaws of the existing ones.
本文分析了现存各种算术编码器结构的缺陷,并提出了一种优化的单输入三级流水线结构。
3.
Compared with the full parallel architecture,the memory cost of the designed processor decreases,thus the speed is higher than that of the SDF pipeline architecture.
该处理器内存资源消耗较并行结构有所减少,运算速度较单独的SDF流水线结构有所提高。
3) Pipeline
[英]['paɪplaɪn] [美]['paɪp'laɪn]
流水线结构
1.
Through pipeline, the latency of decoding process reduces dramatically.
该编译码器采用Euclid算法实现译码 ,编译码过程采用流水线结构提高速率。
2.
This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter(ADC)based on an improved 1.
5位/级结构的10位100MHz流水线结构模数转换器。
3.
A high-speed low-power pipeline A/D converter is designed in this paper.
该文设计了一个高速、低功耗的流水线结构模数转换器(ADC)。
4) pipelined architecture
流水线结构
1.
Radix-4 pipelined architecture is adopted for 16 and 64 points computation.
16,64点运算采用基-4级联流水线结构,256,1 024点采用二维运算结构,数据采用块浮点表示。
2.
Without any other additional circuit, the algorithm achieved a pipelined architecture of rounding method by adjusting the quantization level, the quantization error ranged from -1/2LSB to 1/2LSB.
为了减小流水线结构A/D转换器的量化误差,提出了一种简单有效的改进算法。
3.
This paper adopted the technology of pipelined architecture A/D conversion and designed a A/D convertor of 10 bits resolution factor、10 MSPS sampling speed with nine-stage pipelined architecture of 1.
5位,共9级的流水线结构,可以实现-1/4Vref ~ +1/4Vref范围内的负冗余纠错。
5) parallel pipeline architecture
并行流水线结构
1.
The algorithm is calculated on a parallel pipeline architecture hardware platform which consists of two TMS320C25 chip.
该算法运行于一个双TMS320C25的并行流水线结构硬件平台上。
6) pipelined circuit structure
流水线电路结构
补充资料:SNYG型灌装机流水线
在SNYG灌装机的基础上,可以配置不干胶贴标机(单面贴、双面贴两种)旋压盖机(或自动理盖机,自动加盖机和自动旋盖机)在桶口使用铝箔可以起到保质和防伪的效果,配置FL系列铝箔感应封口机,进行生产日期的喷码(进口代理喷码设备),最后装箱使用装箱机和包装带捆扎机,然后在纸箱上进行纸箱日期喷码。 |
说明:补充资料仅用于学习参考,请勿用于其它任何用途。
参考词条