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1)  path delay fault
通路时延故障
1.
Learning-based test generation for path delay fault of conditional sum adders;
学习策略实现的条件和加法器通路时延故障测试生成
2.
The problem of path delay fault test is addressed in this paper for parallel-prefix tree-like adders,which are kinds of high-speed adders.
时延故障对高速运算电路性能有着关键性的影响,本文对其中之一的并行前置树型加法器的通路时延故障测试作了研究。
3.
This paper gives a survey of the recent development of path delay testing,introduces the classification of single path delay faults according to testability,and analyses three approaches to reducing the number of paths to be tested during path delay testin
本文对目前通路时延测试领域的主要研究成果进行了综述 ,阐述了主要的通路时延可测试性及相应的单通路时延故障的分类 ,并介绍了三种精简通路集的通路时延测试方
2)  delay fault
时延故障
1.
A Test Generation Algorithm for Delay Fault Based on I_(DDT) Test;
一种基于I_(DDT)测试的时延故障测试产生算法
3)  delay fault
延时故障
1.
All delay faults and logic faults can be detected.
本文提出的可编程逻辑器件易测试方法,充分利用了PLD本身固有的可编程特点,简化了器件故障诊断的难度;所有延时、逻辑故障全部可以检测,对延时故障和交叉点故障具有诊断功能,故障检测、诊断十分简
4)  delay fault test
时延故障测试
1.
The problem of path delay fault test is addressed in this paper for parallel-prefix tree-like adders,which are kinds of high-speed adders.
时延故障对高速运算电路性能有着关键性的影响,本文对其中之一的并行前置树型加法器的通路时延故障测试作了研究。
2.
With the rapid development of semiconductor technolology, the integration degree and the operation speed are increasing which lead to delay fault test becoming increasingly critical.
本文研究了算术运算电路的通路时延故障测试。
5)  delay fault testing
延时故障测试
6)  path delay fault
路径时滞故障
1.
A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题,提出了基于神经网络的数字电路路径时滞故障测试生成算法。
2.
A path delay fault testing generation algorithm based on Boolean difference for digital circuits is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题提出了一种基于布尔差分的数字电路路径时滞故障测试生成算法。
补充资料:怀卢延让(时延让新及第)
【诗文】:
冥搜忍饥冻,嗟尔不能休。几叹不得力,到头还白头。
姓名归紫府,妻子在沧洲。又是蝉声也,如今何处游。



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【出处】:
全唐诗:卷834-22
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