1) CRC
循环冗余校验
1.
Implementation of parallel CRC based on FPGA
基于FPGA的循环冗余校验并行实现
2.
This paper introduces the algorithm,theory and checking regulations of CRC,analyzes the computational process of CRC,takes CRC-16 as an example and gives some of the source program of hardware description language Verilog HDL to achieve CRC-16.
介绍了循环冗余校验CRC算法原理和校验规则,分析了CRC校验码的具体计算过程,并以CRC-16为例,给出了使用硬件描述语言Verilog HDL来实现CRC-16的部分源程序,它既是校验码的生成器,也是待校验数据的校验器,对该例进行仿真并给出综合结果,最终可以在现场可编程门阵列(FPGA)上实现,其工作频率可达400 MHz。
3.
For the CRC(Cyclic Redundancy Check) code in frame format,an 8-bit parallel CRC logical circuit is designed through detailed calculation and derivation and implemented in FPGA(Field Programmable Gate Array),which is simulated under MAX + PlusⅡ.
针对帧格式中的循环冗余校验(CRC)校验码,通过详细的计算推导,设计出8位并行CRC逻辑电路并应用于现场可编程门阵列(FPGA),在MAX+PlusⅡ环境下进行了仿真,与串行CRC相比,并行CRC的编码速度大为提高。
2) cyclic redundancy check
循环冗余校验
1.
Realization of the Cyclic Redundancy Check through User-defined Custom Instructions on SOPC;
循环冗余校验在SOPC中的自定义指令实现
2.
Research of File Protection with Cyclic Redundancy Check;
循环冗余校验CRC在文件保护中的研究
3.
Based on the principles and the characteristics of Cyclic Redundancy Check,the problems with CRC-16 s programme algorithm and programme realization have been analysed,and its reliability and validity have been testified by using LabVIEW technology.
在论述循环冗余校验的原理和特点的基础上,采用LabVIEW技术,分析和研究了CRC-16程序算法和程序实现的问题,验证了它的可靠性和高效性。
6) cyclical redundancy check
循环冗余位校验
1.
The characteristic of this system is that cyclical redundancy check is employed to ensure higher speed and better reliability in data transmission.
通信中采用了循环冗余位校验(CRC16)方法,保证了数据高速、可靠传输。
补充资料：循环系统的进化鱼的循环系统
李瑞端绘
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说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条